Automatic holistic energy-aware design methodology for MLP neural network hardware generation
This work proposes AHEAD: an automatic holistic energy-aware design methodology for multilayer perceptron (MLP) neural network hardware generation in edge devices. By taking a holistic analysis of the design flow, the approach makes judicious use of the intelligent bit-width identification (BWID) and configurable hardware generation, which autonomously integrate to generate the low-power hardware decoder. The proposed AHEAD methodology begins with the trained MLP parameters and golden datasets and produces an efficient hardware design in terms of performance, power, and area (PPA) with the least loss of accuracy. The results show that the proposed methodology is up to a 4X faster in performance, 3X lower in terms of power consumption, and achieves a 5X reduction in area resources, with exact accuracy, compared to floating-point and half-floating-point design on a field-programmable gate array (FPGA), which makes it a promising design methodology for edge devices. For more details see Huang et al., Energies, 2020.
Autobot for effective design space exploration and agile generation of RBFNN hardware accelerator in embedded real-time computing
We propose a novel Autobot to replace humans in the task of hardware design and implementation of radial basis function neural network (RBFNN) for real-time computing applications. The Autobot can generate mixed-precision hardware architecture and perform hardware design space exploration to facilitate the trade-off analysis between real-time performance and area consumption. The Autobot has been tested with the problem of RBFNN-based Mackey-Glass chaotic time series prediction and servo motor control. The proposed Autobot methodology is a useful alternative for agile real-time hardware development on FPGA. For more details see Huang et al., 2020 IEEE International Conference on Real-time Computing and Robotics (RCAR), 2020.
End-to-End rapid FPGA prototyping for proactive BMI control
We propose an end-to-end rapid prototyping methodology that performs automated and efficient mapping of desired neural networks onto FPGA. The design automation agent is considered as Autobot. An early prototype with the hardware decoder generated on the FPGA has been built, and its functionality has been evaluated. The experimental results show that Autobot can offer rapid end-to-end prototyping for neural network hardware generation for proactive BMI control. For more details see Huang et al., IEEE International Conference on Consumer Electronics – Taiwan (ICCE-Taiwan), 2020.
A scalable echo state networks hardware generator for embedded systems using high-level synthesis
This work presents the design and implementation of a hardware generator for RC-ESNs (echo state networks) to tackle the problem. The proposed methodology is demonstrated by various offline-trained network parameters and topologies. Compared to existing solutions, the proposed framework provides scalability with the support of DSE in agile hardware design. For more details see Huang et al., The 8th Mediterranean Conference on Embedded Computing – MECO’2019.
Hardware implementation of neural networks using high-level synthesis in less than four hours
We introduce the motivation and design of a mini-course to teach hardware implementation of neural networks using high-level synthesis (HLS) in less than four hours for engineering education of intelligent embedded computing. By standing on the shoulders of giants, the combination of the real-world problem, decoding the process of neural networks hardware design, and using HLS as a hands-on lab, the students are able to not only pick up the underlying concepts of digital system design naturally but also implement a real working neural networks hardware accelerator in person. Thus, the main contribution of the work is to facilitate the engineering education of hardware design more engaging and practical. For more details see Huang et al., 20th International Carpathian Control Conference (ICCC), 2019.